The present invention relates generally to integrated circuit devices and packaging methods, and, more particularly, to a method and apparatus forming stacked die and substrate structures for increased packing density.
As microelectronic packaging becomes physically more compact, the amount of “real estate” available on circuit boards and other component-supporting substrates becomes ever smaller. Various die packaging schemes have thus evolved in order to promote greater component density. For example, integrated circuits packaged in plastic or ceramic packages may include extended metal leads for soldering onto a printed circuit board or for insertion into a socket. In many cases, a single package will contain a single integrated circuit, although multiple chips are more commonly being manufactured within a single package. The use of such multiple chips in individual packages results in a low circuit density as a single integrated circuit ceramic or plastic package consumes relatively large areas of real estate on the circuit boards, particularly where a socket is used.
Multi-chip Module (MCM) packaging technology has also been developed to suit applications where it is necessary to reduce the size of the assembly or where speed or electrical noise considerations require shorter connecting leads. A typical multi chip module package combines a number of individual or unpackaged integrated circuits and directly attaches them to a mounting surface (e.g., ceramic substrate, printed circuit board or other substrate). Integrated circuits within MCM assemblies may be electrically connected using various bonding techniques such as soldering, wire bonding, and flip-chip technologies. Many MCM assemblies are generally constructed in a dense two-dimensional array to minimize the surface area otherwise occupied by many individually packaged devices mounted on circuit boards.
It has, however, been recognized that it may be desirable in certain applications to enhance circuit density by vertically stacking dies and substrates in two or more layers. In one approach to vertical stacking, for example, a stack of semiconductor dice may be formed by attaching flip chip mounted die to flexible printed circuit films that are in turn attached to frames. The films are stacked and thereafter encapsulated by a liquid encapsulant that flows around the stack of dice. However, in such a configuration, there is no effective means for cooling any of the die, thus limiting the amount of power the die in such an assembly can dissipate. Certain other organic packages are typically implemented with folded layer designs, which suffer from poor thermal spreading abilities and poor mechanical handling behavior as flexible films.
On the other hand, other vertically stacked modules can provide both high speed processing and cooling capability by attaching micro-miniature heat sink devices (having internal groves for passing coolant therethrough) to the high-power chips such as CPUs. The lower power chips, such as memory chips for example, are simply stacked on top of one another through solder bump connections. Although this type of configuration provides vertical integration and cooling capacity for some of the chips, the packaging density is still limited in that the undersides of the overlying and underlying substrates are not array interconnected.
Accordingly, it would be desirable to provide a stacked die and substrate apparatus having increased packing density and performance, as well as improved cooling capability for both high power die and low power die such as embedded memory or memory included on application specific integrated circuits (ASICs).